Designers are using every design trick to reduce power in a 3G chip design. But, while cutting power, these tricks can create static timing analysis problems. Here's a look at how designers can close ...

With the rapid move to ultradeep submicron designs and feature size processes of 0.13 micron and below, ensuring the integrity of signals as they traverse conductors on a chip is becoming a challenge.

Static timing analysis is a technique of computing of cell delay and interconnect delay in design (known as path delay) and comparing it against constrain (timing specific) set in SDC file. This paper ...

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address ...

Signoff of a system on chip (SoC) or IP design has multiple aspects, but often timing closure is the most challenging. Early use of a static timing analysis (STA) tool is clearly important, and such a ...

What to do, what to do? Chip complexity continues to grow and design schedules are more aggressive, yet design teams are staying the same size or even being scaled back. Something has to give. A key ...